Tutorial T3B: Engineering Change Order (ECO) Phase Challenges and Methodologies for High Performance Design

Engineering Change Order or ECO phase is always challenging for any family of chip design. High Performance Microprocessors are largest and most complex overall design within Semiconductor Industry as a whole. To add further, there are additional design and methodology challenge related to bleeding edge of process nodes. Hence, current and future microprocessor design requires a set of well planned and innovative methodologies to cater to the ECO requirement when the race to the finishing line begins! This tutorial is organized into following four key sections. Apart from that, there will be a brief preview section and a real scenario-based learning section towards the end. ECO Readiness Indicator: Before a design can actually entire ECO phase, quite a few things needs to be assessed. Some of the key indicators are logic and verification stability from front-end team, timing, power, routability, noise and other metrics from backend or circuit team. ECO phase can achieve only limited set of changes and hence design stability needs to be thoroughly evaluated. Also, during mainstream design closure process, ECO preparatory study and optimizations need to be performed. Typically it includes ensuring sufficient ECO resource availability following a good distribution in all part of design. ECO resources include spare latch, Gate-Array cells among others. ECO Variants: After ensuring ECO readiness indicators are achieved, designers need to know nature of ECO requests that might come in. This can be categorized based on timeline (full stack comprising of device and metal stack usage for ECO or limited metal stack usage type) or based on ECO objective. Typically, there are two basic flavor of ECO objective –Functional or Performance based. Functional ECOs arise because of last moment verification bugs caught or critical enhancement components. Performance based ECOs occur for different changes made to optimize timing across hierarchical boundary, change in timing constraints or other dependent changes. There can be minor but other kind of requests related to power, noise etc. CAD for ECO: ECO CAD framework typically consists of a ECO extraction engine, ECO stitching and ECO physical synthesis engine. ECO extraction engine uses a SAT solver based functional equivalence checker, logic structural matching algorithm internally. ECO stitcher merges the ECO logic elements to original Netlist but it is not synthesized and placed yet. ECO physical synthesis segment perform actual physical synthesis optimization ECO implementation. This engine opens up a limited logic cone (1or 2hop neighborhood) in ECO delta region for timing/power/other convergence criteria. Finally, incremental ECO routing is performed to build the complete 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems 1063-9667/14 $31.00 © 2014 IEEE DOI 10.1109/VLSID.2014.118 7 design. ECO Implementation Strategies: After the ECO requirements are analyzed in terms of technical challenge, risks and time in hand, a suitable methodology is adopted to get it done. On a broader level, it is taken through either a ECO tool based methodology or manual ECO methodology. Sometime both approach are tried in parallel to save time. ECO tool based methodology typically supports multiple CAD recipes depending on ECO complexity, amount of change requested for most efficient ECO solution that comes with least change in design. Manual ECO approach on the other hand counts on skill of individual engineer identifying the ECO location and getting functional equivalence or timing targets achieved after the changes made. Post ECO Design Closure: After primary objective of the ECO is met, the entire design needs to be taken through a set of quality checks to make sure it is of tape-out quality. In most cases, there will be secondary optimizations based on additional design violations created while trying to achieve primary ECO needs. These violations are fixed in subsequent design iterations.